Doped Silicon Wafer Arsenic Doped
CN β US| HS Code | Tariff Rate | Origin | Destination | Doc |
|---|---|---|---|---|
| 8541590040 | 60.0% | CN | US | Official Doc |
| 2804695000 | 15.5% | CN | US | Official Doc |
| 2804691000 | 15.3% | CN | US | Official Doc |
| 8541100040 | 60.0% | CN | US | Official Doc |
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π§ͺ Doped Silicon Wafer (Arsenic Doped)
π HS Code Reference & Customs Clearance Guide | 2026 Latest Tariff Full Analysis | Professional Clearance Strategy
π I. Product Definition & Classification: Do You Really Understand "Arsenic-Doped Silicon"?
Arsenic-doped silicon wafers are the foundational raw materials for semiconductor manufacturing. They consist of high-purity silicon crystals doped with arsenic atoms to create N-type semiconductors. In international trade, classification hinges on two critical factors: State of Processing (raw material vs. processed wafer) and Material Nature (elemental silicon vs. semiconductor device component).
Two Main Classification Paths: 1. Semiconductor Raw Material (Wafers/Chips): If the product is a processed wafer intended for use as a base for semiconductor devices, it falls under Chapter 85. 2. Elemental Silicon Material: If the product is considered a semi-finished elemental silicon material (sheet form) without specific semiconductor device integration, it may fall under Chapter 28.
β οΈ Key Distinction:
- If described as "unmounted wafers," "chips," or "grains" for semiconductor devices β Chapter 85 (8541.59.00.40 / 8541.10.00.40)
- If described as "sheet-shaped semi-finished elemental silicon" β Chapter 28 (2804.69.50.00 / 2804.69.10.00)
π¦ II. HS Code Classification Details (2026 Latest Tariff Authority Comparison)
| HS Code | Product Description | Application Scenario | Key Classification Logic |
|---|---|---|---|
8541.59.00.40 |
Doped silicon wafers (Arsenic-doped); semiconductor material; wafer/chip form; unmounted wafers classification | Semiconductor base raw materials; processed wafers ready for device fabrication | β High Value-Added/Processed |
8541.10.00.40 |
Silicon material; wafer/chip form; unmounted chips, grains, and wafers classification | Base raw materials for semiconductor devices; specifically unmounted | β Specific Semiconductor Sub-category |
2804.69.50.00 |
Core material is silicon; sheet-shaped semi-finished product; other silicon classification | Elemental silicon in sheet form; less processed than wafers | β Raw/Semi-finished Elemental |
2804.69.10.00 |
Material is silicon; sheet-shaped; fits classification logic for "other silicon" | General sheet-shaped silicon products; basic elemental form | β Basic Elemental Form |
π Critical Reminder:
- Chapter 85 (8541.xx) applies when the silicon is doped and shaped as a wafer for semiconductor use. This is the most common and accurate classification for arsenic-doped wafers. - Chapter 28 (2804.69) applies only if the product is considered elemental silicon material in sheet form, lacking the specific characteristics of a semiconductor wafer (e.g., precise doping profiles, surface finish for photolithography). - Misclassification Risk: Declaring a processed semiconductor wafer as "elemental silicon" (2804) may lead to customs scrutiny or rejection, as it does not reflect the product's true industrial purpose.
π° III. 2026 Latest Tariff Rate Breakdown (Including Surtaxes & Policy Add-ons)
β Applicable Country: United States (US)
β Origin: China (CN)
β Effective Date: From November 10, 2025 (including subsequent imports)
π― 1. 8541.59.00.40 ββ Doped Silicon Wafer (Arsenic Doped)
| Item | Content |
|---|---|
| Base Tariff | 0.0% (ad valorem) |
| USITC Surtax (Section 301) | +50.0% |
| 122 Section Tariff | +10.0% |
| Total Tariff | 60.0% |
| Tax Calculation | CIF Value Γ 60.0% |
| De Minimis Exemption Eligibility | β Not Eligible |
| Legal Basis Path | Section 301: 8541.59.00.40 β Section 122: 10% |
π Explanation:
- The 50% USITC surtax is imposed under Section 301 of the Trade Act of 1974, targeting specific Chinese-origin goods, including semiconductor-related silicon products. - The 10% 122 Section tariff is an additional surcharge applicable to certain imports from China. - Total 60% is an extremely high tariff. This category captures the high value-added nature of processed semiconductor wafers.
π― 2. 8541.10.00.40 ββ Unmounted Chips, Grains, and Wafers
| Item | Content |
|---|---|
| Base Tariff | 0.0% (ad valorem) |
| USITC Surtax (Section 301) | +50.0% |
| 122 Section Tariff | +10.0% |
| Total Tariff | 60.0% |
| Tax Calculation | CIF Value Γ 60.0% |
| De Minimis Exemption Eligibility | β Not Eligible |
| Legal Basis Path | Section 301: 8541.10.00.40 β Section 122: 10% |
π Note:
- Identical tax structure to8541.59.00.40. - This code is used if the product is specifically classified as "unmounted chips, grains, and wafers" rather than general doped wafers. - 60% total rate remains constant.
π― 3. 2804.69.50.00 ββ Other Silicon (Sheet Semi-finished)
| Item | Content |
|---|---|
| Base Tariff | 5.5% |
| USITC Surtax (Section 301) | 0.0% |
| 122 Section Tariff | +10.0% |
| Total Tariff | 15.5% |
| Tax Calculation | CIF Value Γ 15.5% |
| De Minimis Exemption Eligibility | β Possible (if under $800 and not excluded) |
| Legal Basis Path | Section 301: None for this subheading β Section 122: 10% |
π Note:
- Significantly lower tariff (15.5%) compared to Chapter 85 codes. - However, this classification is only valid if the product is legally deemed "elemental silicon" in sheet form, not a functional semiconductor wafer. - Using this code for a functional arsenic-doped wafer carries high compliance risk.
π― 4. 2804.69.10.00 ββ Other Silicon (Sheet Form)
| Item | Content |
|---|---|
| Base Tariff | 5.3% |
| USITC Surtax (Section 301) | 0.0% |
| 122 Section Tariff | +10.0% |
| Total Tariff | 15.3% |
| Tax Calculation | CIF Value Γ 15.3% |
| De Minimis Exemption Eligibility | β Possible (if under $800 and not excluded) |
| Legal Basis Path | Section 301: None for this subheading β Section 122: 10% |
π Note:
- Similar to2804.69.50.00, this is a low-tariff category for elemental silicon. - Do not use if the product is clearly a semiconductor wafer.
π οΈ IV. Customs Clearance Practical Advice (Real-World Pitfall Avoidance Guide)
β 1. Required Documentation Checklist (All Required)
| Document | Mandatory | Description |
|---|---|---|
| β Product Specification Sheet | βοΈ | Must include doping concentration (arsenic %, cmβ»Β³), resistivity, wafer thickness, diameter, crystal orientation. |
| β Certificate of Origin (CO) | βοΈ | To verify Chinese origin and apply applicable surtaxes. |
| β Commercial Invoice | βοΈ | Must clearly state "Arsenic-Doped Silicon Wafer" and intended use (e.g., "for semiconductor device fabrication"). |
| β Packing List | βοΈ | Detail wafer quantity, packaging type (FOUP/box), and weights. |
| β Technical Data Sheet (TDS) | βοΈ | Proves product is a semiconductor-grade wafer, not raw silicon. |
| β FCC/CE Certifications (if applicable) | βοΈ | Not always required for raw wafers, but good for compliance tracking. |
β 2. Declaration Strategy (Key Mantra)
π₯ βWafer = Chapter 85; Raw Sheet = Chapter 28; Name Precisely, Avoid High Tariff Trap!β
| Scenario | Correct Declaration | Incorrect Practice |
|---|---|---|
| Processed Arsenic-Doped Wafer | 8541.59.00.40 or 8541.10.00.40 |
Misdeclare as 2804.69.50.00 β High risk of audit, penalty, or seizure |
| Raw Silicon Sheet (Non-semiconductor) | 2804.69.50.00 |
Misdeclare as 8541.59.00.40 β Unnecessary 60% tariff |
| Mixed Shipment (Wafers + Raw Silicon) | Separate HS Codes | Mix under one HS Code β Customs rejection |
| Small Sample (< $800) | Check De Minimis Eligibility | Assume all silicon is exempt β Penalty if misclassified |
β 3. Special Case Handling
| Scenario | Handling Advice |
|---|---|
| OEM Custom Wafers | Provide customer PO + technical specs to prove specific doping/profile. |
| Wafer + Packaging Only | Declare as wafer (8541.59.00.40). Packaging is incidental. |
| Argon-Doped vs. Arsenic-Doped | Both fall under Chapter 85 if semiconductor-grade. Arsenic is N-type. |
| Re-exported from Third Country | Origin rules still apply. If processed in CN, US surtaxes likely apply. |
π V. Global Market Clearance Comparison (2026 Latest)
| Country/Region | Recommended HS Code | Tariff Rate | Certification Requirements | Notes |
|---|---|---|---|---|
| πΊπΈ USA | 8541.59.00.40 |
60.0% | None (but strict origin verification) | Highest tariff globally for this product. |
| π¨π³ China | 8541.59.00.40 |
~0-5% | RoHS, REACH (if exported) | No surtaxes. |
| πͺπΊ EU | 8541.10.00 |
~0-4% | REACH, RoHS | No Section 301-style surtaxes. |
| π―π΅ Japan | 8541.10.00 |
~0-3% | PSE (if device) | Lower tariffs than US. |
| π°π· South Korea | 8541.10.00 |
~0-5% | KC Mark (if device) | Free Trade Agreement benefits may apply. |
π Conclusion:
- USA imposes the highest effective tariff (60%) due to Section 301 and 122 surtaxes. - Other markets have significantly lower or zero tariffs. - Supply Chain Strategy: Consider sourcing from non-China origins (e.g., USA, EU, Japan) for US-bound shipments to avoid surtaxes, or adjust pricing to absorb the 60% cost.
π VI. Common Mistakes & Pitfall Guide (Blood & Tears Lessons)
β Mistake 1: Declaring arsenic-doped wafers as "Silicon Raw Material" (2804) to save on tariffs.
π Consequence: Customs inspection will reveal semiconductor-grade characteristics β Back taxes, penalties, and potential import ban.
β Mistake 2: Failing to declare "Arsenic Doped" in commercial invoice.
π Consequence: Ambiguity leads to customs reclassification β Delays and additional duties.
β Mistake 3: Assuming all silicon products are exempt from de minimis.
π Consequence: If classified under 2804 and shipped under $800, it might be exempt, but if classified under 8541, it is never exempt for Chinese origin.
β Mistake 4: Using incorrect HS Code for "unmounted" vs. "mounted" wafers.
π Consequence: If wafers are already mounted on substrates, they may fall under 8542.31 or other codes, changing tax treatment.
β Correct Approach:
"Arsenic-Doped N-Type Silicon Wafer, 8-inch, 200mm, Semiconductor Grade, For IC Fabrication, Doping Concentration: 1x10^18 cmβ»Β³, Model: ASW-200-A"
π― VII. Conclusion: Professional Declaration, Save Time, Reduce Costs!
π― Remember the Mantra:
πΉ "Wafer is Semiconductor (8541), Raw Silicon is Element (2804); 60% Tax in USA, 15% in Raw Category; Name Precisely, Avoid Audit Trap!"
πΉ "HS Code Determines Fate, 45% Difference in Tax, One Step Wrong, Thousands in Penalties!"
π Pro Tip:
If your silicon wafers are originally from the USA, Germany, Japan, or South Korea, you may avoid the 50% Section 301 surtax, reducing the total tariff to 10% (122 Section only) or lower, depending on the specific code and trade agreements.
Recommendation: Apply for a Binding Ruling (Advance Ruling) from US Customs and Border Protection (CBP) to confirm the correct HS Code and tax liability before shipment.
π£ Take Action Now:
π Contact Professional Customs Brokers + Provide Technical Specs + Apply for HS Code Advance Ruling
π Ensure Your Silicon Wafers, Smooth Clearance, Efficient Export, Maximized Profit!
β¨ Professional Clearance Starts with Accurate Classification!
πΌ Every Cent of Your Cost Deserves Precise Calculation!
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About HS Code Classification
The Harmonized System (HS) is an internationally standardized nomenclature developed by the World Customs Organization (WCO) to classify traded products. Over 200 countries use the HS system as the basis for customs tariffs, trade statistics, and import/export regulations.
Each HS code follows a hierarchical structure:
- Chapter (2 digits) β Broad category of goods (e.g., Chapter 84: Machinery and Mechanical Appliances)
- Heading (4 digits) β More specific grouping within the chapter
- Subheading (6 digits) β Internationally standardized breakdown, used by all WCO member countries
- National subdivisions (8-10 digits) β Country-specific extensions for further classification, such as US HTSUS 10-digit codes
Correct HS code classification is essential for smooth customs clearance, accurate duty payment, and compliance with trade regulations. Misclassification can lead to customs delays, overpayment of duties, or penalties.
When importing from CN to US, the applicable tariff rates may include:
- Most-Favored-Nation (MFN) rate β The standard duty rate applied to WTO members
- General rate β Applied to countries without trade agreements
- Trade remedy duties β Additional tariffs such as Section 301 (anti-dumping), Section 232 (national security), or countervailing duties
The information provided on this page is for reference purposes only. For official classification, please consult with your local customs authority or a licensed customs broker.